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september 2011 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 FSD176MRT ? green-mode fairchild power switch (fps?) FSD176MRT green-mode fairchild power switch (fps?) features ? advanced soft burst-mode operation for low standby power and low audible noise ? random frequency fluctuation for low emi ? pulse-by-pulse current limit ? various protection functions: overload protection (olp), over-voltage protection (ovp), abnormal over-current protection (aocp), internal thermal shutdown (tsd) with hysteresis, output-short protection (osp), and under-voltage lockout (uvlo) with hysteresis ? low operating current (0.4ma) in burst mode ? internal startup circuit ? internal high-voltage sensefet: 650v ? built-in soft-start: 15ms ? auto-restart mode applications ? power supply for lcd monitor, stb, and dvd combination description the FSD176MRT is an in tegrated pulse width modulation (pwm) controller and sensefet specifically designed for offline switch-mode power supplies (smps) with minimal external components. the pwm controller includes an in tegrated fixed-frequency oscillator, under-voltage lockout (uvlo), leading- edge blanking (leb), optimized gate driver, internal soft-start, temperature-co mpensated precise current sources for loop compensation, and self-protection circuitry. compared with a discrete mosfet and pwm controller solution, the FSD176MRT can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. this device provides a basic platform for cost-effective design of a flyback converter. ordering information part number package operating junction temperature current limit r ds(on) (max.) output power table (2) replaces device 230v ac 15% (3) 85~265v ac adapter (4) open frame (5) adapter (4) open frame (5) FSD176MRTudtu to-220 6-lead (1) u-forming -40c ~ +125c 3.50a 1.6 ? 80w 90w 48w 70w fsgm0765r FSD176MRTldtu to-220 6-lead (1) l-forming -40c ~ +125c 3.50a 1.6 ? 80w 90w 48w 70w fsgm0765r notes: 1. pb-free package per jedec j-std-020b. 2. the junction temperature can limit the maximum output power. 3. 230v ac or 100/115v ac with voltage doubler. 4. typical continuous power in a non-v entilated enclosed adapt er measured at 50 ? c ambient temperature. 5. maximum practical continuous power in an open-frame design at 50 ? c ambient temperature.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 2 FSD176MRT ? green-mode fairchild power switch (fps?) application circuit ac in v str drain gnd fb v cc v o figure 1. typical application circuit internal block diagram t on ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 3 FSD176MRT ? green-mode fairchild power switch (fps?) pin configuration figure 3. pin configuration (top view) pin definitions pin # name description 1 drain sensefet drain . high-voltage power sensefet drain connection. 2 gnd ground . this pin is the control ground and the sensefet source. 3 v cc power supply . this pin is the positive supply input, which provides the internal operating current for both startup and steady-state operation. 4 fb feedback . this pin is internally connected to t he inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stabl e operation, a capacitor should be placed between this pin and gnd. if the voltage of this pin r eaches 7v, the overload protection triggers, whic h shuts down the fps. 5 nc no connection 6 v str startup . this pin is connected directly, or thr ough a resistor, to the high-voltage dc link. at startup, the internal high- voltage current source supplies internal bias and charges the external capacitor connected to the v cc pin. once v cc reaches 12v, the internal current source (i ch ) is disabled.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 4 FSD176MRT ? green-mode fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v str v str pin voltage 650 v v ds drain pin voltage 650 v v cc v cc pin voltage 26 v v fb feedback pin voltage - 0.3 12.0 v i dm drain current pulsed 12.8 a i ds continuous switching drain current (6) t c =25 ? c 6.4 a t c =100 ? c 4.0 a e as single pulsed avalanche energy (7) 390 mj p d total power dissipation (t c =25 ? c) (8) 50 w t j maximum junction temperature 150 ? c operating junction temperature (9) - 40 +125 ? c t stg storage temperature - 55 +150 ? c esd electrostatic discharge capability human body model, jesd22-a114 4.5 kv charged device model, jesd22-c101 2.0 notes: 6. repetitive peak switching current when the inductive load is assumed: limited by maximum duty (d max =0.74) and junction temperature (see figure 4. ) . 7. l=45mh, starting t j =25 ? c. 8. infinite cooling condition (refer to the semi g30-88) . 9. although this parameter guarantees ic operation, it does not guarantee all electr ical characteristics. figure 4. repetitive peak switching current thermal impedance t a =25c unless otherwise specified. symbol parameter value unit ja junction-to-ambient thermal impedance (10) 63.5 c/w jc junction-to-case thermal impedance (11) 2.5 c/w notes: 10. free standing without heat sink under natural convection condi tion, per jedec 51-2 and 1-10. 11. infinite cooling condition per mil std. 883c method 1012.1.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 5 FSD176MRT ? green-mode fairchild power switch (fps?) electrical characteristics t j = 25 ? c unless otherwise specified. symbol parameter conditions min. typ. max. unit sensefet section bv dss drain-source breakdown voltage v cc = 0v, i d = 250 ? a 650 v i dss zero-gate-voltage drain current v ds = 650v, t a = 25 ? c 250 ? a r ds(on) drain-source on-state resistance v gs =10v, i d =1a 1.3 1.6 ? c iss input capacitance (12) v ds = 25v, v gs = 0v, f=1mhz 674 pf ? c oss output capacitance (12) v ds = 25v, v gs = 0v, f=1mhz 93 pf ? t r rise time v ds = 325v, i d = 4a, r g =25 ? 30 ns ? t f fall time v ds = 325v, i d = 4a, r g =25 ? 26 ns ? t d(on) turn-on delay v ds = 325v, i d = 4a, r g =25 ? 16 ns t d(off) turn-off delay v ds = 325v, i d = 4a, r g =25 ? 39 ns control section f s switching frequency (12) v cc = 14v, v fb = 4v 61 67 73 khz ? f s switching frequency variation (12) - 25 ? c < t j < 125 ? c 5 10 % d max maximum duty ratio v cc = 14v, v fb = 4v 61 67 73 % d min minimum duty ratio v cc = 14v, v fb = 0v % i fb feedback source current v fb =0v 65 90 115 ? a v start uvlo threshold voltage v fb = 0v, v cc sweep 11 12 13 v v stop after turn-on, v fb = 0v 7.0 7.5 8.0 v t s/s internal soft-start time v str = 40v, v cc sweep 15 ms burst-mode section v burh burst-mode voltage v cc = 14v, v fb sweep 0.39 0.45 0.51 v v burl 0.26 0.30 0.34 v v hys 150 mv protection section i lim peak drain current limit di/dt = 300ma/ ? s 3.15 3.50 3.85 a v sd shutdown feedback voltage v cc = 14v, v fb sweep 6.45 7.00 7.55 v i delay shutdown delay current v cc = 14v, v fb = 4v 1.2 2.0 2.8 ? a t leb leading-edge blanking time (12)(14) 300 ns v ovp over-voltage protection v cc sweep 23.0 24.5 26.0 v t osp output-short protection (12) threshold time osp triggered when t on v osp (lasts longer than t osp_fb ) 0.7 1.0 1.3 ? s v osp threshold v fb 1.8 2.0 2.2 v t osp_fb v fb blanking time 2.0 2.5 3.0 ? s tsd thermal shutdown temperature (12) shutdown temperature 130 140 150 ? c t hys hysteresis 60 ? c continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 6 FSD176MRT ? green-mode fairchild power switch (fps?) electrical characteristics (continued) t j = 25 ? c unless otherwise specified. symbol parameter conditions min. typ. max. unit total device section i op operating supply current, (control part in burst mode) v cc = 14v, v fb = 0v 0.3 0.4 0.5 ma i ops operating switching current, (control part and sensefet part) v cc = 14v, v fb = 2v 1.1 1.5 1.9 ma i start start current v cc =11v (before v cc reaches v start ) 85 120 155 ? a i ch startup charging current v cc = v fb = 0v, v str = 40v 0.7 1.0 1.3 ma v str minimum v str supply voltage v cc = v fb = 0v, v str sweep 26 v notes: 12. although these param eters are guaranteed, t hey are not 100% tested in production. 13. average value. 14. t leb includes gate turn-on time. comparison of fsgm0765r and FSD176MRT function fsgm0765r FSD176MRT advantages of FSD176MRT random frequency fluctuation built - in low emi operating current 1.6ma 0. 4ma very low standby power
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 7 FSD176MRT ? green-mode fairchild power switch (fps?) typical performance characteristics characteristic graphs are normalized at t a =25c. 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 5. operating supply current (i op ) vs. t a figure 6. operating switching current (i ops ) vs. t a 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 7. startup charging current (i ch ) vs. t a figure 8. peak drain current limit (i lim ) vs. t a 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 9. feedback source current (i fb ) vs. t a figure 10. shutdown delay current (i delay ) vs. t a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 8 FSD176MRT ? green-mode fairchild power switch (fps?) typical performance characteristics characteristic graphs are normalized at t a =25c. 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 11. uvlo threshold voltage (v start ) vs. t a figure 12. uvlo threshold voltage (v stop ) vs. t a 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 13. shutdown feedback voltage (v sd ) vs. t a figure 14. over-voltage protection (v o v p ) vs. t a 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 20'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 15. switching frequency (f s ) vs. t a figure 16. maximim duty ratio (d max ) vs. t a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 9 FSD176MRT ? green-mode fairchild power switch (fps?) functional description 1. startup: at startup, an inter nal high-voltage current source supplies the inter nal bias and charges the external capacitor (c vcc ) connected to the v cc pin, as illustrated in figure 17. when v cc reaches 12v, the FSD176MRT begins switching and the internal high- voltage current source is disabled. the FSD176MRT continues normal switching operation and the power is supplied from the auxiliary transformer winding unless v cc goes below the stop voltage of 7.5v. figure 17. startup block 2. soft-start : the internal soft-start circuit increases the pwm comparator inverting i nput voltage, together with the sensefet current, slowly after startup. the typical soft-start time is 15ms. the pulse width to the power switching device is progressi vely increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressive ly increased to smoothly establish the requir ed output voltage. th is helps prevent transformer saturation and reduces stress on the secondary diode during startup. 3. feedback control : this device employs current- mode control, as shown in figure 18. an opto-coupler (such as the fod817) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cy cle. when the reference pin voltage of the shunt regulat or exceeds the internal reference voltage of 2.5v, t he opto-coupler led current increases, pulling down the feedback voltage and reducing drain current. this typically occurs when the input voltage is increased or the output load is decreased. 3.1 pulse-by-pulse current limit : because current- mode control is employed, the peak current through the sensefet is limited by the inverting input of the pwm comparator (v fb *), as shown in figure 18. assuming that the 90 a current source flows only through the internal resistor (3r + r = 27k ? ), the cathode voltage of diode d2 is about 2.5v. since d1 is blocked when the feedback voltage (v fb ) exceeds 2.5v, the maximum voltage of the cathode of d2 is clamped at this voltage. ther efore, the peak value of the current through the sensefet is limited. 3.2 leading-edge blanking (leb) : at the instant the internal sensefet is tur ned on, a high-current spike usually occurs through the sensefet, caused by primary-side capacitance and secondary-side rectifier reverse recovery. excessi ve voltage across the r sense resistor leads to incorre ct feedback operation in the current-mode pwm control. to counter this effect, the FSD176MRT employs a leading-edge blanking (leb) circuit. this circuit inhibits the pwm comparator for t leb (300ns) after the sensefet is turned on. figure 18. pulse width modulation circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 10 FSD176MRT ? green-mode fairchild power switch (fps?) 4. protection circuits : the FSD176MRT has several self-protective functions, su ch as overload protection (olp), abnormal over-current protection (aocp), output-short protection (osp) , over-voltage protection (ovp), and thermal shutdown (tsd). all the protections are implemented as auto-restart. once a fault condition is detected, switching is terminated and the sensefet remains off. this causes v cc to fall. when v b cc b falls to the under-voltage lockout (uvlo) stop voltage of 7.5v, the pr otection is reset and the startup circuit charges the v cc capacitor. when v cc reaches the start voltage of 12.0v, the FSD176MRT resumes normal operation. if the fault condition is not removed, the sensefet remains off and v cc drops to stop voltage again. in this manner, the auto-restart can alternately enable and disabl e the switching of the power sensefet until the faul t condition is eliminated. because these protection circ uits are fully integrated into the ic without external components, the reliability is improved without increasing cost. figure 19. auto-restart protection waveforms 4.1 overload protection (olp) : overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. in this situation, the protection circuit should tri gger to protect the smps. however, even when the smps is in normal operation, the overload pr otection circuit can be triggered during load transition. to avoid this undesired operation, t he overload protection circuit is designed to trigger only after a specified time to determine whether it is a tr ansient situation or a true overload situation. becaus e of the pulse-by-pulse current limit capability, the maximum peak current through the sensefet is lim ited and, ther efore, the maximum input power is restricted with a given input voltage. if the output cons umes more than this maximum power, the output voltage (v out ) decreases below the set voltage. th is reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor curr ent, thus increasing the feedback voltage (v fb ). if v fb exceeds 2.5v, d1 is blocked and the 2.0a current source starts to charge c fb slowly up . in this condition, v fb continues increasing until it reaches 7.0v, when the switching operation is terminated, as shown in figure 20. the delay for shutdown is the time required to charge c fb from 2.5v to 7.0v with 2.0 a. a 25 ~ 50ms delay is typical for most applications. this protection is implemented in auto-restart mode. figure 20. overload protection 4.2 abnormal over-current protection (aocp) : when the secondary rect ifier diodes or the transformer pins are short ed, a steep current with extremely high di/dt can flow through the sensefet during the minimum turn-on time. overload protection is not enough to protect t he FSD176MRT in that abnormal case; since severe current stress is imposed on the sensefet unt il olp is triggered. the FSD176MRT internal aocp circuit is shown in figure 21. when the gate turn-on signal is applied to the power sensefet, the aocp block is enabled and monitors the current through the sensing resistor. the voltage across the resistor is compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level, the se t signal is applied to the s - r latch, resulting in t he shutdown of the smps. figure 21. abnormal over-current protection
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 11 FSD176MRT ? green-mode fairchild power switch (fps?) 4.3. output-short protection (osp) : if the output is shorted, steep current with extremely high di/dt can flow through the sensefet during the minimum turn- on time. such a steep current brings high-voltage stress on the drain of the sensefet when turned off. to protect the device from this abnormal condition, osp is included. it is comprised of detecting v fb and sensefet turn-on time. when the v fb is higher than 2.0v and the sensefet turn-on time is lower than 1.0 s, the FSD176MRT recognizes this condition as an abnormal error and shuts down pwm switching until v cc reaches v start again. an abnormal condition output short is shown in figure 22. figure 22. output-short protection 4.4 over-voltage protection (ovp): if the secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto-coupler transistor becomes almost zero. then v fb climbs up in a similar manner to the overload situat ion, forcing the preset maximum current to be supplied to the smps until the overload protection is tri ggered. because more energy than required is provided to the output, the output voltage may exceed the ra ted voltage before the overload protection is tri ggered, resulting in the breakdown of the devices in the secondary side. to prevent this situation, an o vp circuit is employed. in general, the v cc is proportional to the output voltage and the FSD176MRT uses v cc instead of directly monitoring the output voltage. if v cc exceeds 24.5v, an ovp circuit is triggered, resulting in the termination of the switching operat ion. to avoid undesired activation of ovp during normal operation, v cc should be designed to be below 24.5v. 4.5 thermal shutdown (tsd) : the sensefet and the control ic on a die in one package makes it easier for the control ic to detect the over temper ature of the sensefet. if the temperature exceeds ~140 ? c, the thermal shutdown is tri ggered and stops operation. the FSD176MRT operates in auto-restart mode until the temperature dec reases to around 75 ? c, when normal operation resumes. 5. soft burst-mode operation : to minimize power dissipation in standby mode, the FSD176MRT enters burst-mode operation. as the load decreases, the feedback voltage decreases. t he device automatically enters burst mode when t he feedback voltage drops below v burl (300mv), as shown in figure 23. at this point, switching stops and t he output voltages start to drop at a rate dependent on st andby current load. this causes the feedback voltage to rise. once it passes v burh (450mv), switching resumes. the feedback voltage then falls and the pr ocess repeats. burst mode alternately enables and dis ables switching of the sensefet, reducing switching loss in standby mode. figure 23. burst-mode operation 6. random frequency fluctuation (rff) : fluctuating switching frequency of an smps can reduce emi by spreading the energy over a wide frequency range. the amount of emi reduction is directly related to the switching frequency variation, which is limited internally. the switching frequency is determined randomly by external feedback voltage and an internal free-running oscillator at every switching instant. this random frequency fluctuation scatters the emi noise around typical switching frequency (67khz) effectively and can reduce the cost of the input filter in cluded to meet the emi requirements (e.g. en55022). figure 24. random frequency fluctuation
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 12 FSD176MRT ? green-mode fairchild power switch (fps?) typical application circuit application input voltage rated output rated power lcd monitor 85 ~ 265v ac 5.0v (3a) 64w power supply 14.0v (3.5a) key design notes: 1. the delay for overload protection is designed to be about 30ms with c105 (8.2nf). olp time between 39ms (12nf) and 46ms (15nf) is recommended. 2. the smd-type capacitor (c106) must be placed as close as possible to the v cc pin to avoid malfunction by abrupt pulsating noises and to improve esd and sur ge immunity. capacitance between 100nf and 220nf is recommended. figure 25. schematic
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 13 FSD176MRT ? green-mode fairchild power switch (fps?) transformer specification ? core: eer3019 (a e =134 mm 2 ) ? bobbin: eer3019 figure 26. transformer specification table 1. winding specification pin(s f) wire turns winding method barrier tape top bot ts n p /2(bot) 3 2 0.4 1 18 solenoid winding 2.0mm 1 insulation: polyester tape t = 0.025mm, 2 layers n 5v 7 6 0.4 3 (tiw) 3 solenoid winding 3.0mm 1 insulation: polyester tape t = 0.025mm, 2 layers n a 4 5 0.20 1 8 solenoid winding 4.0mm 3.0mm 1 insulation: polyester tape t = 0.025mm, 2 layers n 5v 8 6 0.4 3 (tiw) 3 solenoid winding 3.0mm 1 insulation: polyester tape t = 0.025mm, 2 layers n 14v 10 8 0.4 3 (tiw) 5 solenoid winding 1 insulation: polyester tape t = 0.025mm, 2 layers n p /2(top) 2 1 0.4 1 18 solenoid winding 2.0mm 1 insulation: polyester tape t = 0.025mm, 2 layers table 2. electrical characteristics pin specification remark inductance 1 3 465 ? h 6% 67khz, 1v leakage 1 3 10 ? h maximum short all other pins
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 14 FSD176MRT ? green-mode fairchild power switch (fps?) table 3. bill of materials part # value note part # value note fuse capacitor f101 250v 3.15a c101 220nf/275v box (pilkor) ntc c102 150nf/275v box (pilkor) ntc101 5d-11 dsc c103 120f/400v electrolytic (samyoung) resistor c104 3.3nf/630v film (sehwa) r101 1.5m ? , j 1w c105 12nf/100v film (sehwa) r103 43k ? , j 1w c106 220nf smd (2012) r201 1k ? , f 1/4w, 1% c107 47f/50v electrolytic (samyoung) r202 1.2k ? , f 1/4w, 1% c201 1000f/25v electrolytic (samyoung) r203 18k ? , f 1/4w, 1% c202 1000f/25v electrolytic (samyoung) r204 8k ? , f 1/4w, 1% c203 1000f/25v electrolytic (samyoung) r205 8k ? , f 1/4w, 1% c204 2200f/10v electrolytic (samyoung) c205 1000f/16v electrolytic (samyoung) c206 1000f/16v electrolytic (samyoung) ic c207 100nf smd (2012) c208 100nf smd (2012) smps FSD176MRT fairchild semiconductor c301 4.7nf/y2 y-cap (samhwa) ic201 ka431lz fairchild semiconductor inductor ic301 fod817b fairchild semiconduc tor lf101 20mh line filter 0.5? diode l201 5h 5a rating d101 1n4007 vishay l202 5h 5a rating d102 uf4004 vishay transformer zd101 1n4750 vishay t101 465h d201 mbr20150ct fairchild semiconductor d202 fypf2006dn fairchild semiconductor bd101 g3sba60 vishay
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 15 FSD176MRT ? green-mode fairchild power switch (fps?) physical dimensions notes: a) no package standard applies. b) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. c) dimensions are in millimeters. d) drawing filename : mkt-to220e06rev2 16.08 15.68 ? 3.28 3.08 2.19 1.27 3.81 1.75 0.85 0.75 5plcs 5 5 (0.70) 0.61 0.46 3.18 #2,4,6 #1,3,5 2.74 2.34 #1 #6 r1.00 0.65 0.55 6plcs 3.40 3.20 10.36 9.96 4.90 4.70 6plcs 6.88 6.48 b (1.13) 1.30 1.05 a 0.20 ab c 4.80 4.40 (17.83) (21.01) 0.05 c r1.00 5.18 4.98 figure 27. 6-lead, to220, fullpack, formed package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 16 FSD176MRT ? green-mode fairchild power switch (fps?) physical dimensions 5 5 ? 3.28 3.08 (7.00) 1.75 3.81 1.27 2.19 (0.70) 0.60 0.45 (0.88) (5.40) 10.36 9.96 3.40 3.20 2.74 2.34 19.97 18.97 3.06 2.46 3.48 2.88 16.07 15.67 8.13 7.13 #1 #6 #2,4 #3,5 0.70 0.50 5plcs 0.80 0.70 5plcs 1.40 1.20 24.00 23.00 13.05 7.15 7.29 6.69 #1,6 (3.81) (0.48) a b 5.18 4.98 6.88 6.48 0.20 ab 4.80 4.40 notes: a) no package standard applies. b) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. c) dimensions are in millimeters. d) drawing filename : mkt-to220f06rev2 18.94 17.94 r0.55 r0.55 r0.55 figure 28. 6-lead, to220, fullpack, u-forming, 2 dap package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FSD176MRT ? rev. 1.0.0 17 FSD176MRT ? green-mode fairchild power switch (fps?)

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